The present invention relates to high-output RF power amplifiers and, more particularly, to a push-pull RF power amplifier.
An RF power amplifier for data transmission used in radio communication equipment represented by a mobile phone has been required to be smaller in size and perform a high-output and high-efficiency operation. As an example of means for increasing the output of the power amplifier, there has been known a push-pull power amplifier circuit which operates power amplifying elements composed of a pair of field-effect transistors (TFTs) in phase opposition, combines output signals from the individual FETs, and outputs a resultant signal.
A description will be given herein below to an RF power amplifier according to a first conventional embodiment disclosed in Japanese Unexamined Patent Publication No. HEI 11-251849 with reference to the drawings.
FIG. 4 shows a circuit structure of the push-pull RF power amplifier according to the first conventional embodiment disclosed in the foregoing publication.
As shown in FIG. 4, the RF power amplifier comprises: a power distributing circuit 102 for distributing a signal inputted to an input terminal 101 such that first and second distributed signals having the same amplitude and a phase difference of 180xc2x0 therebetween are outputted therefrom; an amplifier main body portion 103 composed of a pair of FET elements 103a which have a common source and respective gates for receiving the first and second distributed signals, perform power amplification with respect to the first and second distributed signals, and output first and second amplified signals; and a power combining circuit 105 which receives the first and second amplified signals, combines the first and second amplified signals that have been received, and outputs a resultant signal to an output terminal 104.
Between the power distributing circuit 102 and the amplifier main body portion 103, there is provided an input matching circuit 107 for matching the impedance of an input-side device connected to the input terminal 101 and the input impedance of the amplifier main body portion 103 via a pair of input capacitors 106 for interrupting a dc signal which are provided on the input side.
Between the amplifier main body portion 103 and the power combining circuit 105, there is provided an output matching circuit 109 for matching the output impedance of the amplifier main body portion 103 and the impedance of an output-side device connected to the output terminal 104 via a pair of output capacitors 108 for interrupting a dc signal which are provided on the output side.
The input matching circuit 107 is composed of: a pair of microstrip lines 107a connecting each of the input capacitors 106 to the amplifier main body portion 103 in series; and an input matching capacitor 107b for connecting the pair of microstrip lines 107a to each other. Likewise, the output matching circuit 109 is composed of: a pair of microstrip lines 109a for connecting the amplifier main body portion 103 to each of the output capacitors 108 in series; and an output matching capacitor 109b for connecting the pair of microstrip lines 109a to each other.
Gate bias terminals 110 to each of which a gate bias signal is applied are connected to the respective gates of the FET elements 103a of the amplifier main body portion 103 via respective lines 111. The gate bias terminals 110 are grounded via respective capacitors 112.
Likewise, drain bias terminals 113 to each of which a drain bias signal is applied are connected to the respective drains of the FET elements 103a of the amplifier main body portion 103 via respective lines 114. The drain bias terminals 113 are grounded via respective capacitors 115.
A description will be given next to a push-pull RW power amplifier according to a second conventional embodiment with reference to the drawings.
FIG. 5 shows the amplifier main body portion 103 formed on a package 201 prior to sealing. The second conventional embodiment is different from the first conventional embodiment in that the amplifier main body portion 103 is provided with a first tertiary harmonic control circuit 211 and a second tertiary harmonic control circuit 212.
As shown in FIG. 5, the package 201 is provided with: the pair of FET elements 103a; a pair of input terminals 202 for receiving the first and second distributed signals from the power distributing circuit 107 shown in FIG. 4; and a pair of output terminals 203 for outputting the first and second amplified signals. Between the input terminals 202 and the FET elements 103a, there are provided a pair of input terminal electrodes 205 and a pair of internal input matching transmission lines 206 which are electrically connected to each other via bonding wires 204. Likewise, a pair of internal output matching transmission lines 207 and a pair of output terminal electrodes 208 which are electrically connected to each other via bonding wires 204 are provided between the FET elements 103a and the output terminals 203.
A first high dielectric substrate 209 is provided under each of the internal input matching transmission lines 206, while a second high dielectric substrate 210 is provided under each of the internal output matching transmission lines 207.
Each of the internal input matching transmission lines 206 on the first high dielectric substrate 209 is connected to the first tertiary harmonic control circuit 211. The first tertiary harmonic control circuit 211 is constituted by: a pair of microstrip lines 211a having respective one ends connected individually to the internal input matching transmission lines 206; and a chip capacitor 211b interposed between and connected to the respective other ends of the pair of microstrip lines 211a. Each of the microstrip lines 211a has a length corresponding to {fraction (1/12)} of the fundamental wavelength xcex of an input signal.
Likewise, each of the internal output matching transmission lines 207 on the second high dielectric substrate 210 is connected to the second tertiary harmonic control circuit 212. The second tertiary harmonic control circuit 212 is constituted by: a pair of microstrip lines 212a having respective one ends connected individually to the internal output matching transmission lines 207 and a chip capacitor 212b interposed between and connected to the respective other ends of the pair of microstrip lines 212a. Each of the microstrip lines 212a also has a length corresponding to {fraction (1/12)} of the fundamental wavelength xcex of an input signal.
A description will be given herein below to the characteristics of the RF power amplifier circuit according to the second conventional embodiment.
To obtain a high output from each of the FET elements, it is normally required to increase the gate width of the FET element. The increased gate width reduces each of the input/output impedances of the FET element so that the impedance ratio between the FET element and an external matching circuit is increased. As a result, a loss in converting the impedance of the matching circuit is increased disadvantageously.
To prevent the increased loss, the RF amplifier according to the conventional embodiment has the first and second high dielectric substrates 209 and 210 provided in proximity to the input/output terminals 202 and 203 of each of the FET elements 103a, respectively, thereby accomplishing conversion such that the impedance is maximized in the vicinity of the FET element 103a and suppressing a loss in impedance conversion resulting from the matching circuit provided externally. Such a circuit is termed an internal matching circuit because it is provided within the package 201.
As is well known, the first and second distributed signals inputted to each of the FET elements 103a are amplified and outputted. If the inputted signals have large amplitudes, however, the FET element 103a generates not only a fundamental wave but also a harmonic. In addition, the first and second distributed signals have a phase difference of 180xc2x0 therebetween. If comparisons are made between signals at the respective input terminals 202 of the FET elements 103a and between signals at the respective output terminals 203 of the FET elements 103a, each of the fundamental wave and an odd harmonic has a phase difference of 180xc2x0, while an even harmonic has a phase difference of 0xc2x0.
In the second conventional embodiment, the first tertiary harmonic control circuit 211 provided on the input side keeps a load impedance to an odd harmonic at the input terminal 202 at a high value close to the impedance of an open circuit so that each of the FET elements 103a performs F-class operation and a power added efficiency (drain efficiency) is improved.
Likewise, the second tertiary harmonic control circuit 212 provided on the output side keeps a load impedance to an odd harmonic at the output terminal 203 at a high value close to the impedance of an open circuit so that each of the FET elements 103a performs F-class operation and the power added efficiency is improved.
If the gate width of each of the FET elements 103a is increased such that a high output is obtained from the RF power amplifier, the input/output impedances of the FET element 103a are reduced. Consequently, each of the high dielectric substrates 209 and 210 used for the internal matching circuit is required to function as a capacitor with a large capacitance. The capacitance value of the capacitor composed of the high dielectric substrate 209 or 210 is determined by the dielectric constant and thickness of the substrate. Since the dielectric constant is determined by a material, fine adjustment of the capacitance value is performed by adjusting the thickness.
To implement capacitors with large capacitances in the RF power amplifiers according to the first and second conventional embodiments, the thickness of each of the first and second high dielectric substrates 209 and 210 should be reduced so that the substrates are easily broken during mounting in the fabrication process. Another problem is encountered in a back-surface polishing step performed to adjust the thickness of each of the high dielectric substrates 209 and 210. Every time the back-surface polishing step is performed, variations of normally about 10% occur in the thicknesses of the substrates 209 and 210 so that variations also occur in the capacitance values of the capacitors.
Still another problem is encountered in forming the tertiary harmonic control circuits 211 and 212 on the first and second high dielectric substrates 209 and 210, respectively, for higher-efficiency operation. Although the chip capacitors 211b and 212b are used as respective capacitors necessary for the tertiary harmonic control circuits 211 and 212, variations occur in the capacitance values of the chip capacitors. In addition, an extra step of mounting the chip capacitors 211b on the respective high dielectric substrates 209 and 210 should also be performed.
It is therefore a first object of the present invention to allow an easy increase in the capacitance of a capacitor in the internal matching circuit of an RF power amplifier by solving the foregoing conventional problems. A second object of the present invention is to prevent variations in the capacitance of a capacitor in a tertiary harmonic control circuit and obviates the necessity for a mounting step.
To attain the first object, the present invention in one aspect is constructed such that a pair of protruding portions are disposed in mutually spaced apart and opposing relation to produce a capacitance component on a pair of transmission lines corresponding to input and output signals to and from a pair of power amplifying elements performing a push-pull operation.
To attain the second object, the present invention in another aspect is constructed such that a capacitor connected to transmission lines each corresponding to {fraction (1/12)} of a fundamental wavelength is formed from a space between the protruding portions of the transmission lines.
Specifically, an RF power amplifier according to the present invention comprises: a pair of power amplifying elements for receiving first and second distributed signals resulting from distribution of an input signal from the outside and having characteristics of the same amplitude and opposite phases, performing power amplification with respect to each of the first and second distributed signals that have been received, and outputting the first and second amplified signals; and a pair of transmission lines connected correspondingly to the pair of power amplifying elements, the pair of transmission lines having a pair of protruding portions provided at respective edge portions thereof disposed in opposing relation, the pair of protruding portions being disposed in mutually spaced apart and opposing relation to compose a capacitor.
In the RF power amplifier according to the present invention, the opposing edge portions of the pair of transmission lines are provided with the pair of protruding portions opposed to each other with the space provided therebetween such that the capacitor for performing impedance conversion with respect to the pair of power amplifying elements is composed of the protruding portions. By adjusting the space between the protruding portions, therefore, a high-precision capacitor with a large capacitance can be implemented.
Since the pair of protruding portions allow the adjustment of the capacitance value of the capacitor and the position thereof on a substrate, higher-precision impedance matching can be performed with respect to the pair of power amplifying elements.
Preferably, the RF power amplifier according to the present invention further comprises: a capacitance adjusting film composed of a high dielectric material and provided indiscretely over the pair of protruding portions. The arrangement implements a high-precision capacitor with a large capacitance by adjusting the dielectric constant and thickness of the capacitance adjusting film and the position at which it is formed.
In the RF power amplifier according to the present invention, each of the pair of protruding portions preferably has a line length corresponding to about {fraction (1/12)} of a fundamental wavelength of the input signal.
In the arrangement, the capacitor composed of the pair of protruding portions constitutes a tertiary harmonic control circuit. By adjusting the space between the protruding portions or the width of each of the protruding portions, therefore, a high-precision capacitor with an optimum capacitance value can be formed easily. This eliminates variations in the capacitance value of the capacitor and obviates the necessity for a chip capacitor so that the step of mounting the chip capacitor is omitted.
In the RF power amplifier according to the present invention, the pair of transmission lines are preferably formed on respective substrates each composed of a high dielectric material. The arrangement reduces the lengths of the transmission lines and reduces the size of the amplifier.